In the case of a conventional MOS transistor in “bulk” technology, the active zones are directly implanted in a mass (“bulk”) of thick silicon forming the substrate. The presence of a thick substrate that is electrically continuous with the active superficial layers, however, induces parasitic phenomena therein, and makes them sensitive in particular to electrical disturbances (for example, leakage currents toward the substrate).
The special feature of transistors produced according to silicon-on-nothing (SON) technology, by comparison with the conventional “bulk” transistors, is the presence of a thin embedded dielectric layer, which insulates the conductive channel of the transistor from the substrate. The thickness of the thin film of silicon corresponding to the conductive channel of the transistor and of the insulating thin film is typically on the order of 5 to 25 nm. The benefit of such a structure is based in particular on better control of parasitic effects.
The SON technology also makes it possible to produce transistors with dynamic properties that are superior to those of the conventional CMOS technology, in addition to having other clear advantages such as lower consumption.
The advantages of this technology make it particularly suitable for uses in the fields of portable electronic apparatuses and wireless communication devices, which require components with increased performance in terms of speed and low consumption.
There is a need for circuits that are capable of simultaneously integrating components whose functions involves electrical properties specific to “bulk” devices, and components performing faster functions and thus involving electrical properties specific to SON or localized silicon-on-insulator (SOI) devices. Therefore, there is a need to integrate these two types of devices on a single substrate.